This project deals with one of the major issues of concern for the future deep-submicron IC technologies regarding yield, device performance and stability and device and product reliability, namely the mechanical stress built up in the layers and substrate. It is therefore important to give a quantitative account of these stresses and this can only be achieved by disposing of reliable, performant (resolution) and quantitative techniques for the local stress determination in the substrate, of adequate and dedicated process simulation tools and of sensitive methods to analyse the stress effects on device performance.
The main scope of this project is to develop an experimental methodology based on the convergent beam electron diffraction technique of the transmission electron microscopy (TEM/CBED) to measure lattice strain in silicon with a spatial resolution down to 1 nm. The strain tensor will be determined by this technique on structures fabricated on 8” silicon wafers, which will comprise CMOS devices with a linewidth down to 0.15 mm for non volatile memories (NVM).
The methodology of TEM/CBED will be developed in a such a way that the strain tensor can be achieved routinely, starting from the diffraction pattern taken at the electron microscope, through an appropriate software, which will be set up during the project activity. In this way, the methodology will be a useful tool for the microelectronic industry.
The full implementation of the TEM/CBED technique is strictly related to the following objectives:
- Set up of a feedback which uses the results of the strain investigation to modify the technological process flow, in order to minimise the stress in the final 0.15 mm structure.
- Upgrading of stress/strain simulation models in order to reach the accuracy required by deep submicron CMOS technologies. Currently, a quasi complete set of 2D numerical stress/strain models already exists in a few TCAD (Technology Computer Aided Design) systems as well as in 3D for some process steps (annealing). However, these models suffer from a lack of characterisation. Furthermore, for deep submicron CMOS technologies, new sources of stress might be considered. Using stress measurements provided by TEM/CBED electron microscopy technique and results given by simple analytical models, the inadequacies of the models will be assessed. According to the result, new models will be introduced if necessary and the mechanical properties of the materials will be characterised. In this latter case, the Brillouin light scattering technique will be of primary usefulness. Finally, the upgraded simulations models will support the TEM/CBED measurement to set up the feedback to modify the technological process flow of the 0.15 mm CMOS generation in order to minimise stress.
- Improvement of the microRaman technique, which is presently used to measure stress in electronic devices with linewidths down to 1 mm. This technique will be first employed on micron-sized structures which will be realised on purpose: the results of this non destructive technique will be checked against the ones obtained from TEM/CBED. Subsequently, through experimental upgrading and improvement of the image convolution techniques, the microRaman analysis will be extended to structures of decreasing size. In this case the TEM/CBED will be used to check the microRaman results. It is not expected, however, that this technique can be applied to the final 0.15 mm structure.
- Application of a new technique, which can give information on stress and is based on the diffraction of X-rays, generated by an electro-synchrotron. This technique is presently in an exploratory phase and will be developed during the project activity, in order to be able to yield the strain tensor in the structures of interest with the required spatial resolution.
To achieve the objectives of the proposed project, the work has been divided into eight Workpackages.